All Enhanced Extended Regular 12 bits 14 bits 16 bits RAM
size ROM
size EEPROM
size Common
SFRs
Features Configuration Bits RAM map SFR map

PIC12F617
CONFIG (address:0x2007, mask:0x0FFF, default:0x0FFF)
FOSC -- Oscillator Selection bits (bitmask:0x0007)
FOSC = LP | 0x3FF8 | LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT.
FOSC = XT | 0x3FF9 | XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT.
FOSC = HS | 0x3FFA | HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT.
FOSC = EC | 0x3FFB | EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN.
FOSC = INTOSCIO | 0x3FFC | INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN.
FOSC = INTOSCCLK | 0x3FFD | INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN.
FOSC = EXTRCIO | 0x3FFE | EXTRCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN.
FOSC = EXTRCCLK | 0x3FFF | EXTRC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN.
WDTE -- Watchdog Timer Enable bit (bitmask:0x0008)
WDTE = OFF | 0x3FF7 | WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
WDTE = ON | 0x3FFF | WDT enabled.
PWRTE -- Power-up Timer Enable bit (bitmask:0x0010)
PWRTE = ON | 0x3FEF | PWRT enabled.
PWRTE = OFF | 0x3FFF | PWRT disabled.
MCLRE -- MCLR Pin Function Select bit (bitmask:0x0020)
MCLRE = OFF | 0x3FDF | MCLR pin is alternate function, MCLR function is internally disabled.
MCLRE = ON | 0x3FFF | MCLR pin is MCLR function and weak internal pull-up is enabled.
CP -- Code Protection bit (bitmask:0x0040)
CP = ON | 0x3FBF | Program memory is external read and write protected.
CP = OFF | 0x3FFF | Program memory is not code protected.
IOSCFS -- Internal Oscillator Frequency Select (bitmask:0x0080)
IOSCFS = 4MHZ | 0x3F7F | 4 MHz.
IOSCFS = 8MHZ | 0x3FFF | 8 MHz.
BOREN -- Brown-out Reset Selection bits (bitmask:0x0300)
BOREN = OFF | 0x3CFF | BOR disabled.
BOREN = NSLEEP | 0x3EFF | BOR enabled during operation and disabled in Sleep.
BOREN = ON | 0x3FFF | BOR enabled.
WRT -- Flash Program Memory Self Write Enable bits (bitmask:0x0C00)
WRT = ALL | 0x33FF | 000h to 7FFh write protected, entire program memory is write protected.
WRT = HALF | 0x37FF | 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control.
WRT = BOOT | 0x3BFF | 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control.
WRT = OFF | 0x3FFF | Write protection off.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:09 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.