# PM0044 5.4.3 Pipeline with Call/Jump, table 10

Legend
| Decode
| Execute
| Fetch
| Flush
| Fetch Stall - space in prefetch buffer but bus busy
| Decode Stall - bus busy
| Decode Stall - insufficient data in prefetch buffer
| Decode Stall - read after write

PM0044 table 10 shows a fetch stall in the first execution cycle of the call (cycle 7) however it should be possible for a fetch to take place since pushing the return address only busies the data bus (and STM8 is a Harvard architecture with unified address space so the data and program are separate buses).

Also note that since the flush happens on the last execute cycle of the call (unlike the jp) there is no overlap and we mark the following cycle as a decode stall. Technically this is correct but table 10 does not and says the call takes 3 cycles which ignores the unavoidable stall cycle. The later instruction documentation for call says it takes 4 cycles which is presumed to include the stall cycle that follows it.

0x080c4 | inc A |  |  |
0x080c5 | jp 0x80cc |  |  |  |
0x080cc | neg A |  |  |  |  |  |
0x080cd | call 0x80d8 |  |  |  |  |  |  |  |
0x080d8 | incw X |  |  |  |  |  |  |  |  |  |  |
Address | Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---