# PM0044 5.4 Conventions, table 3

Legend
| Decode
| Execute
| Fetch
| Flush
| Fetch Stall - space in prefetch buffer but bus busy
| Decode Stall - bus busy
| Decode Stall - insufficient data in prefetch buffer
| Decode Stall - read after write

## Errata

- The LDW shown in PM0044 table 3 is missing a decode cycle.
  (Confirmed on HW)
- The ADDW shown in PM0044 table 3 has one too many decode cycles.
  (Confirmed on HW)
- The LD shown in PM0044 table 3 is missing a decode cycle.

0x0808c | ldw X,[0x50.w] |  |  |  |  |  |  |
0x0808f | addw X,#0x0014 |  |  |  |  |  |  |  |  |
0x08092 | ld A,[0x30.w] |  |  |  |  |  |  |  |  |  |  |  |  |
Address | Instruction | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---