OPENSSL_RISCVCAP(3ossl)

NAME
OPENSSL_riscvcap - the RISC-V processor capabilities vector

SYNOPSIS
 env OPENSSL_riscvcap=... <application>

DESCRIPTION
libcrypto supports RISC-V instruction set extensions. These extensions are denoted by individual extension names in the capabilities vector. For Linux platform, when libcrypto is initialized, the results returned by the RISC-V Hardware Probing syscall (hwprobe) are stored in the vector. Otherwise all capabilities are disabled.

To override the set of instructions available to an application, you can set the OPENSSL_riscvcap environment variable before you start the application.

The environment variable is similar to the RISC-V ISA string defined in the RISC-V Instruction Set Manual. It is case insensitive. Though due to the limit of the environment variable parser inside libcrypto, an extension must be prefixed with an underscore to make it recognizable. This also applies to the Vector extension.

 OPENSSL_riscvcap="rv64gc_v_zba_zbb_zbs..."

Note that extension implication is currently not implemented. For example, when "rv64gc_b" is provided as the environment variable, zba/zbb/zbs would not be implied in the capability vector.

Currently only these extensions are recognized:

ZBA Address Generation

    Could be detected using hwprobe for Linux kernel >= 6.5

ZBB Basic bit-manipulation

    Could be detected using hwprobe for Linux kernel >= 6.5

ZBC Carry-less multiplication

    Could be detected using hwprobe for Linux kernel >= 6.8

ZBS Single-bit instructions

    Could be detected using hwprobe for Linux kernel >= 6.5

ZBKB
    Bit-manipulation for Cryptography

    Could be detected using hwprobe for Linux kernel >= 6.8

ZBKC
    Carry-less multiplication for Cryptography

    Could be detected using hwprobe for Linux kernel >= 6.8

ZBKX
    Crossbar permutations

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKND
    NIST Suite: AES Decryption

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKNE
    NIST Suite: AES Encryption

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKNH
    NIST Suite: Hash Function Instructions

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKSED
    ShangMi Suite: SM4 Block Cipher Instructions

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKSH
    ShangMi Suite: SM3 Hash Function Instructions

    Could be detected using hwprobe for Linux kernel >= 6.8

ZKR Entropy Source Extension

ZKT Data Independent Execution Latency

    Could be detected using hwprobe for Linux kernel >= 6.8

V   Vector Extension for Application Processors

    Could be detected using hwprobe for Linux kernel >= 6.5

ZVBB
    Vector Basic Bit-manipulation

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVBC
    Vector Carryless Multiplication

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKB
    Vector Cryptography Bit-manipulation

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKG
    Vector GCM/GMAC

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKNED
    NIST Suite: Vector AES Block Cipher

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKNHA
    NIST Suite: Vector SHA-2 Secure Hash

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKNHB
    NIST Suite: Vector SHA-2 Secure Hash

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKSED
    ShangMi Suite: SM4 Block Cipher

    Could be detected using hwprobe for Linux kernel >= 6.8

ZVKSH
    ShangMi Suite: SM3 Secure Hash

    Could be detected using hwprobe for Linux kernel >= 6.8

RETURN VALUES
Not available.

EXAMPLES
Check currently detected capabilities

 $ openssl info -cpusettings
 OPENSSL_riscvcap=RV64GC_ZBA_ZBB_ZBC_ZBS_V vlen:256

Note: The first word in the displayed capabilities is the RISC-V base architecture value, which is derived from the compiler configuration. It is therefore not overridable by the environment variable. When the V extension is given the riscv_vlen value is always displayed, there is no way to override the riscv_vlen by the environment variable.

Disables all instruction set extensions:

 export OPENSSL_riscvcap="rv64gc"

Only enable the vector extension:

 export OPENSSL_riscvcap="rv64gc_v"

COPYRIGHT
Copyright 2024 The OpenSSL Project Authors. All Rights Reserved.

Licensed under the Apache License 2.0 (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.