Features Configuration Bits RAM map SFR map

PIC16LF18455
CONFIG1 (address:0x8007, mask:0x2977, default:0x2977)
FEXTOSC -- External Oscillator mode selection bits (bitmask:0x0007)
FEXTOSC = LP | 0x3FF8 | LP (crystal oscillator) optimized for 32.768kHz; PFM set to low power.
FEXTOSC = XT | 0x3FF9 | XT (crystal oscillator) above 500kHz, below 4MHz; PFM set to medium power.
FEXTOSC = HS | 0x3FFA | HS (crystal oscillator) above 4MHz; PFM set to high power.
FEXTOSC = RESERVED | 0x3FFB | Reserved.
FEXTOSC = OFF | 0x3FFC | Oscillator not enabled.
FEXTOSC = ECL | 0x3FFD | EC below 500kHz; PFM set to low power.
FEXTOSC = ECM | 0x3FFE | EC for 500kHz to 8MHz; PFM set to medium power.
FEXTOSC = ECH | 0x3FFF | EC above 8MHz; PFM set to high power.
RSTOSC -- Power-up default value for COSC bits (bitmask:0x0070)
RSTOSC = HFINT32 | 0x3F8F | HFINTOSC with OSCFRQ= 32 MHz and CDIV = 1:1.
RSTOSC = HFINTPLL | 0x3F9F | HFINTOSC with 2x PLL, with OSCFRQ = 16 MHz and CDIV = 1:1 (FOSC = 32 MHz).
RSTOSC = EXT4X | 0x3FAF | EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
RSTOSC = RESERVED | 0x3FBF | Reserved.
RSTOSC = SOSC | 0x3FCF | SOSC.
RSTOSC = LFINT | 0x3FDF | LFINTOSC.
RSTOSC = HFINT1 | 0x3FEF | HFINTOSC (1MHz).
RSTOSC = EXT1X | 0x3FFF | EXTOSC operating per FEXTOSC bits.
CLKOUTEN -- Clock Out Enable bit (bitmask:0x0100)
CLKOUTEN = ON | 0x3EFF | CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
CLKOUTEN = OFF | 0x3FFF | CLKOUT function is disabled; i/o or oscillator function on OSC2.
CSWEN -- Clock Switch Enable bit (bitmask:0x0800)
CSWEN = OFF | 0x37FF | The NOSC and NDIV bits cannot be changed by user software.
CSWEN = ON | 0x3FFF | Writing to NOSC and NDIV is allowed.
FCMEN -- Fail-Safe Clock Monitor Enable bit (bitmask:0x2000)
FCMEN = OFF | 0x1FFF | FSCM timer disabled.
FCMEN = ON | 0x3FFF | FSCM timer enabled.
CONFIG2 (address:0x8008, mask:0x1EE7, default:0x1EE7)
MCLRE -- Master Clear Enable bit (bitmask:0x0001)
MCLRE = OFF | 0x3FFE | MCLR pin function is port defined function.
MCLRE = ON | 0x3FFF | MCLR pin is Master Clear function.
PWRTS -- Power-up Timer Enable bit (bitmask:0x0006)
PWRTS = PWRT_1 | 0x3FF9 | PWRT set at 1 ms.
PWRTS = PWRT_16 | 0x3FFB | PWRT set at 16 ms.
PWRTS = PWRT_64 | 0x3FFD | PWRT set at 64 ms.
PWRTS = OFF | 0x3FFF | PWRT disabled.
LPBOREN -- Low-Power BOR enable bit (bitmask:0x0020)
LPBOREN = ON | 0x3FDF | ULPBOR enabled.
LPBOREN = OFF | 0x3FFF | ULPBOR disabled.
BOREN -- Brown-out reset enable bits (bitmask:0x00C0)
BOREN = OFF | 0x3F3F | Brown-out reset disabled.
BOREN = SBOREN | 0x3F7F | Brown-out reset enabled according to SBOREN bit.
BOREN = NSLEEP | 0x3FBF | Brown-out Reset enabled while running, disabled in sleep; SBOREN is ignored.
BOREN = ON | 0x3FFF | Brown-out Reset Enabled, SBOREN bit is ignored.
BORV -- Brown-out Reset Voltage Selection (bitmask:0x0200)
BORV = HI | 0x3DFF | Brown-out Reset Voltage (VBOR) is set to 2.7V.
BORV = LO | 0x3FFF | Brown-out Reset Voltage (VBOR) set to 1.9V.
ZCDDIS -- Zero-cross detect disable (bitmask:0x0400)
ZCDDIS = ON | 0x3BFF | Zero-cross detect circuit is always enabled.
ZCDDIS = OFF | 0x3FFF | Zero-cross detect circuit is disabled at POR.
PPS1WAY -- Peripheral Pin Select one-way control (bitmask:0x0800)
PPS1WAY = OFF | 0x37FF | The PPSLOCK bit can be set and cleared repeatedly by software.
PPS1WAY = ON | 0x3FFF | The PPSLOCK bit can be cleared and set only once in software.
STVREN -- Stack Overflow/Underflow Reset Enable bit (bitmask:0x1000)
STVREN = OFF | 0x2FFF | Stack Overflow or Underflow will not cause a reset.
STVREN = ON | 0x3FFF | Stack Overflow or Underflow will cause a reset.
CONFIG3 (address:0x8009, mask:0x3F7F, default:0x3F7F)
WDTCPS -- WDT Period Select bits (bitmask:0x001F)
WDTCPS = WDTCPS_0 | 0x3FE0 | Divider ratio 1:32.
WDTCPS = WDTCPS_1 | 0x3FE1 | Divider ratio 1:64.
WDTCPS = WDTCPS_2 | 0x3FE2 | Divider ratio 1:128.
WDTCPS = WDTCPS_3 | 0x3FE3 | Divider ratio 1:256.
WDTCPS = WDTCPS_4 | 0x3FE4 | Divider ratio 1:512.
WDTCPS = WDTCPS_5 | 0x3FE5 | Divider ratio 1:1024.
WDTCPS = WDTCPS_6 | 0x3FE6 | Divider ratio 1:2048.
WDTCPS = WDTCPS_7 | 0x3FE7 | Divider ratio 1:4096.
WDTCPS = WDTCPS_8 | 0x3FE8 | Divider ratio 1:8192.
WDTCPS = WDTCPS_9 | 0x3FE9 | Divider ratio 1:16384.
WDTCPS = WDTCPS_10 | 0x3FEA | Divider ratio 1:32768.
WDTCPS = WDTCPS_11 | 0x3FEB | Divider ratio 1:65536.
WDTCPS = WDTCPS_12 | 0x3FEC | Divider ratio 1:131072.
WDTCPS = WDTCPS_13 | 0x3FED | Divider ratio 1:262144.
WDTCPS = WDTCPS_14 | 0x3FEE | Divider ratio 1:524299.
WDTCPS = WDTCPS_15 | 0x3FEF | Divider ratio 1:1048576.
WDTCPS = WDTCPS_16 | 0x3FF0 | Divider ratio 1:2097152.
WDTCPS = WDTCPS_17 | 0x3FF1 | Divider ratio 1:4194304.
WDTCPS = WDTCPS_18 | 0x3FF2 | Divider ratio 1:8388608.
WDTCPS = WDTCPS_19 | 0x3FF3 | Divider ratio 1:32.
WDTCPS = WDTCPS_20 | 0x3FF4 | Divider ratio 1:32.
WDTCPS = WDTCPS_21 | 0x3FF5 | Divider ratio 1:32.
WDTCPS = WDTCPS_22 | 0x3FF6 | Divider ratio 1:32.
WDTCPS = WDTCPS_23 | 0x3FF7 | Divider ratio 1:32.
WDTCPS = WDTCPS_24 | 0x3FF8 | Divider ratio 1:32.
WDTCPS = WDTCPS_25 | 0x3FF9 | Divider ratio 1:32.
WDTCPS = WDTCPS_26 | 0x3FFA | Divider ratio 1:32.
WDTCPS = WDTCPS_27 | 0x3FFB | Divider ratio 1:32.
WDTCPS = WDTCPS_28 | 0x3FFC | Divider ratio 1:32.
WDTCPS = WDTCPS_29 | 0x3FFD | Divider ratio 1:32.
WDTCPS = WDTCPS_30 | 0x3FFE | Divider ratio 1:32.
WDTCPS = WDTCPS_31 | 0x3FFF | Divider ratio 1:65536; software control of WDTPS.
WDTE -- WDT operating mode (bitmask:0x0060)
WDTE = OFF | 0x3F9F | WDT Disabled, SWDTEN is ignored.
WDTE = SWDTEN | 0x3FBF | WDT enabled/disabled by SWDTEN bit in WDTCON0.
WDTE = NSLEEP | 0x3FDF | WDT enabled while sleep=0, suspended when sleep=1; SWDTEN ignored.
WDTE = ON | 0x3FFF | WDT enabled regardless of sleep; SWDTEN ignored.
WDTCWS -- WDT Window Select bits (bitmask:0x0700)
WDTCWS = WDTCWS_0 | 0x38FF | window delay = 87.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_1 | 0x39FF | window delay = 75 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_2 | 0x3AFF | window delay = 62.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_3 | 0x3BFF | window delay = 50 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_4 | 0x3CFF | window delay = 37.5 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_5 | 0x3DFF | window delay = 25 percent of time; no software control; keyed access required.
WDTCWS = WDTCWS_6 | 0x3EFF | window always open (100%); no software control; keyed access required.
WDTCWS = WDTCWS_7 | 0x3FFF | window always open (100%); software control; keyed access not required.
WDTCCS -- WDT input clock selector (bitmask:0x3800)
WDTCCS = LFINTOSC | 0x07FF | WDT reference clock is the 31.0kHz LFINTOSC output.
WDTCCS = HFINTOSC | 0x0FFF | WDT reference clock is the 31.25 kHz HFINTOSC.
WDTCCS = SOSC | 0x17FF | WDT reference clock is the 32kHz secondary oscillator.
WDTCCS = SC | 0x3FFF | Software Control.
CONFIG4 (address:0x800A, mask:0x2F9F, default:0x2F9F)
BBSIZE -- Boot Block Size Selection bits (bitmask:0x0007)
BBSIZE = BB64K | 0x3FF8 | * half of user program memory.
BBSIZE = BB32K | 0x3FF9 | * half of user program memory.
BBSIZE = BB16K | 0x3FFA | * half of user program memory.
BBSIZE = BB8K | 0x3FFB | 8192 words boot block size.
BBSIZE = BB4K | 0x3FFC | 4096 words boot block size.
BBSIZE = BB2K | 0x3FFD | 2048 words boot block size.
BBSIZE = BB1K | 0x3FFE | 1024 words boot block size.
BBSIZE = BB512 | 0x3FFF | 512 words boot block size.
BBEN -- Boot Block Enable bit (bitmask:0x0008)
BBEN = ON | 0x3FF7 | Boot Block enabled.
BBEN = OFF | 0x3FFF | Boot Block disabled.
SAFEN -- SAF Enable bit (bitmask:0x0010)
SAFEN = ON | 0x3FEF | SAF enabled.
SAFEN = OFF | 0x3FFF | SAF disabled.
WRTAPP -- Application Block Write Protection bit (bitmask:0x0080)
WRTAPP = ON | 0x3F7F | Application Block write protected.
WRTAPP = OFF | 0x3FFF | Application Block not write protected.
WRTB -- Boot Block Write Protection bit (bitmask:0x0100)
WRTB = ON | 0x3EFF | Boot Block write protected.
WRTB = OFF | 0x3FFF | Boot Block not write protected.
WRTC -- Configuration Register Write Protection bit (bitmask:0x0200)
WRTC = ON | 0x3DFF | Configuration Register write protected.
WRTC = OFF | 0x3FFF | Configuration Register not write protected.
WRTD -- Data EEPROM write protection bit (bitmask:0x0400)
WRTD = ON | 0x3BFF | Data EEPROM write protected.
WRTD = OFF | 0x3FFF | Data EEPROM NOT write protected.
WRTSAF -- Storage Area Flash Write Protection bit (bitmask:0x0800)
WRTSAF = ON | 0x37FF | SAF write protected.
WRTSAF = OFF | 0x3FFF | SAF not write protected.
LVP -- Low Voltage Programming Enable bit (bitmask:0x2000)
LVP = OFF | 0x1FFF | High Voltage on MCLR/Vpp must be used for programming.
LVP = ON | 0x3FFF | Low Voltage programming enabled. MCLR/Vpp pin function is MCLR.
CONFIG5 (address:0x800B, mask:0x0001, default:0x0001)
CP -- UserNVM Program memory code protection bit (bitmask:0x0001)
CP = ON | 0x3FFE | UserNVM code protection enabled.
CP = OFF | 0x3FFF | UserNVM code protection disabled.

This page generated automatically by the device-help.pl program (2022-01-30 15:56:10 UTC) from the 8bit_device.info file (rev: 1.44) of mpasmx and from the gputils source package (rev: svn Unversioned directory). The mpasmx is included in the MPLAB X.