Internet-Draft Transport and Services Working Group October 2026
Chen, et al. Expires 3 May 2027 [Page]
Workgroup:
Internet Research Task Force
Internet-Draft:
draft-chen-tsvwg-high-speed-ip-data-express-00
Published:
Intended Status:
Informational
Expires:
Authors:
D. Chen
China Mobile
Z. Li
China Mobile
H. Yang
China Mobile

High speed data express in IP: Concept, Reference Architecture and Technologies

Abstract

With the rapid development of AI technology, intelligent computing and super-computing services, the demand for wide-area transmission of massive data is increasing. This draft makes full use of the advantages of IP network, such as statistical reuse and elastic supply, and proposes a reference architecture of high elasticity and high throughput data express based on IP network.

Requirements Language

The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this document are to be interpreted as described in RFC 2119 [RFC2119].

Status of This Memo

This Internet-Draft is submitted in full conformance with the provisions of BCP 78 and BCP 79.

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This Internet-Draft will expire on 3 May 2027.

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Table of Contents

1. Introduction

With the rapid development of AI technology, intelligent computing, and super-computing services, the demand for wide-area transmission of massive data is increasing. How to transfer a large amount of data quickly, efficiently and conveniently has become an important problem that needs to be solved in the development of communication networks. With the network bandwidth from 10G to 25G, 100G, 200G and even 400G, bandwidth is not the bottleneck of data transmission, the key to data transmission is how to make full use of large bandwidth to achieve efficient throughput.

In most cases, the effective throughput is less than the throughput, which in turn is less than the bandwidth. Bandwidth refers to the number of bits that can be transmitted per second on the link, which depends on the link clock rate and channel coding, also known as line speed (network device transmission capacity). Throughput refers to the actual amount of data transmitted on the bandwidth (terminal device transmission capacity). Goodput refers to the throughput that truly meets service requirements, excluding invalid packets such as retransmission and discarding (service data transmission capability).

In-depth analysis shows that the data transmission throughput performance is mainly affected by five factors: transmission distance, network packet loss rate, effective data length , sending window and the impact factor. As the transmission distance increases, RTT (round trip delay) increases. In reliable transmission mode, the reply time of ACK acknowledgement messages becomes longer, and the sending sliding window cannot be adjusted in time. Network packet loss rate will affect the rate adjustment of congestion control algorithm, and increase the tail delay of data transmission. Effective data length refers to the effective data length of the packet header removed, which can be regarded as MSS. Increasing MSS will help improve throughput. The sending window affects the duration of continuous data sending. If the window is too small, data will be sent before the ACK reply is completed, and sending will be paused. The impact factor F is a comprehensive parameter, such as the CPU frequency, PCIE rate, disk I/O rate, and bandwidth that affect the packet processing rate, 0<F<1, if these have no impact, the value of F is 1. In summary, we can draw the following conclusion: in addition to improving the network environment (improving the physical bandwidth, etc.), the end-to-end data sending and receiving mechanism and transmission protocol are also a key part of the effective throughput.

In order to improve the data transmission efficiency and reduce the data transmission cost as much as possible, we propose to build a highly elastic and high-throughput data transmission network based on IP network, and use elastic bandwidth, load balancing, security encryption and other technologies to realize new data express services.

2. Reference Architecture

The data express solution enables massive data transmission from the data source to the destination. Data sources are devices or systems that generate or store large amounts of data, such as enterprise servers, databases, and storage devices. Data sources can be multiple nodes distributed across different geographies and network environments, or they can be a single node concentrated in one location. Data destination refers to the device or system that receives or processes a large amount of data, such as cloud computing platform, intelligent computing center, and supercomputing center. The data destination can be a public service provided by a third party or a cloud data center built by a data express operator.

Based on the massive transmission requirements from the data source to the destination end, the overall architecture of the data express solution is designed according to the hierarchical idea, which mainly includes three parts: cloud private network infrastructure, network controller and data express operation platform, as shown in

                         +--------------------+
                         |                    |
                         |    Data Express    |
          Task  -------> | Operation Platform |
        Delivery         |                    |
                         +---------+----------+
                                   |
                        +----------+-----------+
                        |                      |
        +---------------+  Network Controller  +---------+
        |               |                      |         |
        |               +-----------+----------+         |
        |                           |                    |
        |                           |                    |
+-------+---------------------------+--------------------+----------+
|                                                                   |
| +-----------+                                       +-----------+ |
| |Data Source|                                       |  Super    | |
| |  Memory   |                                +------+ Computing | |
| | card/disk |                Wide Area       |      |  Center   | |
| +-----+-----+     +------+Interconnection +--+--+   +-----------+ |
|       |           |Cloud +----------------+Cloud|                 |
|       |           |  PE  |                | PE  |                 |
|       |           +---+--+                +--+--+   +-----------+ |
| +-----v------+        |                      |      |  General  | |
| |Data Express|        |                      +------+ Computing | |
| |  Station   +--------+                             |   Center  | |
| +------------+                                      +-----------+ |
|                                                                   |
|                      Infrastructure                               |
+-------------------------------------------------------------------+

3. Core Operation

This section elaborates the workflow and interaction logic of functional components defined in the reference architecture of Section 2. The whole operation follows the high-speed IP data express(HSDE) objective introduced in Section 1, realizing task scheduling, rate regulation and RDMA transmission support within the constraints of the reference architecture.

An HSDE task represents a discrete transmission request submitted by an upper-layer application. Each task is associated with a set of administrative parameters including priority, target SLA, resource quota, and destination endpoint identifier.

The HSDE Task Manager performs admission control for incoming tasks. A task MAY be admitted only if sufficient quota and QP resources are available. Once admitted, the task enters the ready queue waiting for transmission arbitration by the scheduler. Tasks that fail admission MAY be queued for later retry or rejected according to implementation policy.

The HSDE scheduler is the central arbitration component. It takes candidate rate recommendations from congestion control, applies per-task SLA constraints, remaining resource quotas, and per-QP rate guard bounds, and computes a final target sending rate for each selected task.

The scheduler serializes transmission opportunities across competing HSDE tasks. Rate outputs from the scheduler are delivered to the RDMA sender for packet posting. The scheduler does not interpret the source of transport feedback; it operates on abstract loss, RTT, and progress signals.

The congestion control module computes a desired sending rate based on feedback samples collected from the transport datapath. This rate recommendation is submitted to the HSDE scheduler for final arbitration. The congestion control module MUST respect the rate guard limits associated with the target QP. The scheduler retains the authority to cap or adjust the recommended rate to satisfy SLA and quota rules.

HSDE maintains a shared pool of reusable RC QPs to serve concurrent tasks. The QP pool implements the transport resource management capability described in the reference architecture of Section 2. A QP is assigned to one HSDE task at a time. When a task completes or is preempted, the QP context is reset and returned to the pool for reassignment to a subsequent task.

QP reset is implementation-specific, but it MUST clear all task-specific transport state associated with the prior HSDE task before the QP is reused.

The baseline feedback mechanism for HSDE uses native RDMA RC AETH acknowledgments, corresponding to the RDMA feedback path in the Section 2 architecture. The receiver generates standard AETH completion messages to report acknowledged PSN progress. These AETH messages are processed by the sender to advance send credits, update RTT estimates, and detect packet loss.

Loss signals and acknowledgment progress from baseline AETH are delivered into the HSDE Feedback Collector for consumption by congestion control and scheduler logic.

4. Windowless ACK Extension

As illustrated in the reference architecture of Section 2, HSDE defines a standardized interface for RDMA feedback. The T/C-AETH specified herein is an optional alternative implementation of this feedback component, targeting the massive high-speed data transmission goal introduced in Section 1. This extension preserves the layering, component partition and inter-component interfaces of the original reference architecture.

HSDE targets high-throughput RDMA transmission over IP networks. Native RC AETH acknowledgments introduce non-negligible control-plane overhead under high line rates. The traditional ACK windowing logic can also increase feedback latency, which degrades the responsiveness of congestion control for large-flow HSDE tasks.

The T/C-AETH mechanism is designed to reduce acknowledgment overhead and deliver timely loss and timing feedback for HSDE flows, while remaining compatible with the core HSDE scheduling and rate-control architecture.

Support for T/C-AETH is a per-QP capability negotiated during QP setup. Negotiation uses private or vendor-specific QP attributes. No new standard RDMA attributes are defined by this document.

If both initiator and responder signal support for T/C-AETH, the QP MAY enter windowless ACK mode. If negotiation fails, the endpoints MAY retry negotiation within the same QP-setup procedure. Once T/C-AETH mode is successfully enabled for a QP, the ACK mode MUST NOT change for the remaining lifetime of that QP. A QP that does not enable T/C-AETH uses the baseline RC AETH feedback path.

This specification defines only the logical fields of a T/C-AETH message. It does not mandate a fixed binary wire encoding or bit-level layout. Implementations MAY select suitable encoding schemes.

A valid T/C-AETH logically contains:

An empty segment list indicates that the receiver reports acknowledgment progress and timing information, with no newly detected loss intervals.

When operating in T/C-AETH mode, the receiver maintains an ongoing list of detected loss intervals for the QP. When new acknowledgment progress covers existing loss intervals, the covered intervals are removed from the pending segment list.

If the local storage allocated for the segment list is exhausted, older loss intervals MUST be discarded first; newer loss intervals are retained with higher priority. Any loss information discarded this way relies on the standard RDMA timeout mechanism for recovery.

T/C-AETH SHOULD be piggybacked onto outgoing RDMA response packets when a response is available. If no response packet is pending, the receiver MAY send a standalone T/C-AETH control packet. Standalone T/C-AETH packets SHOULD be assigned higher transmit priority to reduce feedback latency.

Malformed or out-of-spec T/C-AETH packets received by the receiver MUST be silently discarded. Discarding such packets MUST NOT alter QP state. Recovery for any associated loss depends on RDMA timeout.

Upon receiving a valid T/C-AETH message, the sender updates its tracked highest acknowledged PSN by taking the maximum value among all received highest-ack-psn fields.

The sender translates the segment list, acknowledged progress, and timestamp into loss events, progress updates, and RTT samples. These signals are forwarded to the HSDE Feedback Collector.

When a QP operating in T/C-AETH mode is reused for a new HSDE task, all T/C-AETH-specific context associated with the prior task MUST be cleared before the new task begins transmission.

Feedback produced by T/C-AETH is injected into the same HSDE Feedback Collector defined in the Section 2 architecture. The scheduler and congestion control module consume abstract feedback signals and remain agnostic to whether the underlying acknowledgment comes from standard AETH or from T/C-AETH.

The T/C-AETH extension does not modify the HSDE scheduler arbitration rules, quota enforcement logic, or QP pool lifecycle semantics described above.

Lost T/C-AETH control messages do not trigger a dedicated recovery procedure. Unresolved loss detection and recovery for the flow MUST rely on the native RDMA timeout mechanism defined for RC QPs.

5. Summary

TBD

6. Security Considerations

TBD.

7. IANA Considerations

This document has no requests to IANA.

8. Normative References

[RFC2119]
Bradner, S., "Key words for use in RFCs to Indicate Requirement Levels", BCP 14, RFC 2119, DOI 10.17487/RFC2119, , <https://www.rfc-editor.org/info/rfc2119>.

Authors' Addresses

Danyang Chen
China Mobile
Beijing
100053
China
Zhiqiang Li
China Mobile
Beijing
100053
China
Hongwei Yang
China Mobile
Beijing
100053
China