B310_FPGA &#x1F517;

0x000000

CORE_SIGNATURE

offset=0x0000

Total Offset =

0x000000

Initial Value not specified

This register is defined in HDL source file basic_regs.sv.

This register contains the unique signature of the MB. This signature is the same value as the one stored on the board ID EEPROM

Bits	Name
31..24	Reserved
23..16	Reserved
15..0	BOARD_ID Board ID corresponds to the las 16 digits of the motherboard part number.

Offset 0x0004: CORE_REVISION Register (R) 🔗

(showhide extended info)

0x000000

CORE_REVISION

offset=0x0004

Total Offset =

0x000004

Initial Value not specified

This register is defined in HDL source file basic_regs.sv.

This register contains the revision number of the current build

Bits	Name
31..24	CURRENT_REV_MAJOR Major version number of the current build
23..16	CURRENT_REV_MINOR Minor version number of the current build
15..0	CURRENT_REV_BUILD Build number of the current build

Offset 0x0008: CORE_OLDEST_REVISION Register (R) 🔗

(showhide extended info)

0x000000

CORE_OLDEST_REVISION

offset=0x0008

Total Offset =

0x000008

Initial Value not specified

This register is defined in HDL source file basic_regs.sv.

This register contains the revision number of the oldest compatible revision

Bits	Name
31..24	OLDEST_REVISION_MAJOR Major version number of the oldest compatible revision
23..16	OLDEST_REVISION_MINOR Minor version number of the oldest compatible revision
15..0	OLDEST_REVISION_BUILD Build number of the oldest compatible revision

Offset 0x0010: CORE_SCRATCH Register (R|W) 🔗

(showhide extended info)

0x000000

CORE_SCRATCH

offset=0x0010

Total Offset =

0x000010

Initial Value = 0x00000000

This register is defined in HDL source file basic_regs.sv.

Read/write scratch register

31..0

SCRATCH_REG (initialvalue=0)

Returns the value written here previously.

Offset 0x0014: GIT_HASH_REGISTER Register (R) 🔗

(showhide extended info)

0x000000

GIT_HASH_REGISTER

offset=0x0014

Total Offset =

0x000014

Initial Value not specified

This register is defined in HDL source file basic_regs.sv.

Git hash of commit used to build this image.
Value equals 0xDEADBEEF if the git hash was not used during synthesis.

31..28

GIT_CLEAN

0x0 in case the git status was clean
0xF in case there were uncommitted changes

27..0

GIT_HASH

7 hex digit hash code of the commit

CORE_REGS_REGMAP 🔗

CORE_REGS_REGISTERS 🔗

This regmap contains general control registers for the FPGA core.

CLOCKING_SPI_SLAVES Enumeration 🔗

Mapping of the SPI slaves on the FPGA core.

Value		Name
Dec	Hex	Name
0	0x0	CLOCKING_SPI_LMK04832_SS
1	0x1	CLOCKING_SPI_TCXO_DAC_SS
2	0x2	CLOCKING_SPI_LMK053_SS

This enumerated type is defined in HDL source file core_regs.sv.

CORE_COMPATIBILITY Enumeration 🔗

Mapping of the SPI slaves on the FPGA core.

Value		Name
Dec	Hex	Name
1	0x1	CORE_COMPAT_MINOR_VAL
2	0x2	CORE_COMPAT_MAJOR_VAL

This enumerated type is defined in HDL source file core_regs.sv.

Offset 0x0000: FPGA_DEVICE_ID Register (R|W) 🔗

(showhide extended info)

0x000020

FPGA_DEVICE_ID

offset=0x0000

Total Offset =

0x000020

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Sets the device ID of the FPGA core. This is used to enumerate the device in RFNoC.

Bits	Name
31..24	Reserved
23..16	Reserved
15..0	DEVICE_ID Device ID.

Offset 0x0004: CORE_SW_RESETS Register (W) 🔗

(showhide extended info)

0x000020

CORE_SW_RESETS

offset=0x0004

Total Offset =

0x000024

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Controls soft-resets across the FPGA

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..1	Reserved
0w	RADIO_CLK_GEN_RST Resets clocking resources for radio clock generation.

Offset 0x0008: CORE_CLOCK_CTRL Register (W) 🔗

(showhide extended info)

0x000020

CORE_CLOCK_CTRL

offset=0x0008

Total Offset =

0x000028

Initial Value = 0x00000001

This register is defined in HDL source file core_regs.sv.

Miscellaneous clock control register.

Bits	Name
31..24	Reserved
23..17	Reserved
16w	USE_EXTERNAL_PPS Selects if the FPGA should use the internal PPS signal for its timekeeping.
15..14	Reserved
13w	LMK05318_PD_N Controls the power down pin to the LMK05318 chip. 0 = power down. 1 = power up.
12w	LMK_RESET Controls the reset pin on the LMK clock generator.
11..9	Reserved
8w	TCXO_EN Enable external TCXO oscillator.
7..5	Reserved
4w	LMK_SOURCE_SELECT Selects the LMK clock source. 0 = 122.88MHz, 1 = 125MHz
3..1	Reserved
0w	REF_CLK_SOURCE (initialvalue=1) Selects the reference clock source. 0 = GPSDO, 1 = Internal.

Offset 0x000C: CORE_CLOCK_STATUS Register (R) 🔗

(showhide extended info)

0x000020

CORE_CLOCK_STATUS

offset=0x000C

Total Offset =

0x00002C

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Miscellaneous clock status register.

Bits	Name
31..24	Reserved
23..16	Reserved
15..9	Reserved
8	LMK_LOCK_STATUS Reports the lock status of the LMK clock generator.
7..0	Reserved

Offset 0x0010: DEVICE_DNA_LOW Register (R) 🔗

(showhide extended info)

0x000020

DEVICE_DNA_LOW

offset=0x0010

Total Offset =

0x000030

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the lower 32 bits of the device DNA.

31..0

DEV_DNA_LO

DNA low bits.

Offset 0x0014: DEVICE_DNA_HIGH Register (R) 🔗

(showhide extended info)

0x000020

DEVICE_DNA_HIGH

offset=0x0014

Total Offset =

0x000034

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the upper 32 bits of the device DNA.

31..0

DEV_DNA_HI

DNA high bits.

Offset 0x0018: CORE_COMPAT_NUM Register (R) 🔗

(showhide extended info)

0x000020

CORE_COMPAT_NUM

offset=0x0018

Total Offset =

0x000038

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the compatibility number for the core.

31..16

CORE_MAJOR_COMPAT

Major compatibility number.

15..0

CORE_MINOR_COMPAT

Minor compatibility number.

Offset 0x001C: CORE_RFNOC_INFO Register (R) 🔗

(showhide extended info)

0x000020

CORE_RFNOC_INFO

offset=0x001C

Total Offset =

0x00003C

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the RFNoC Core settings.

31..16

RFNOC_CHDR_WIDTH

RFNoC CHDR width.

15..0

RFNOC_PROTO_VERSION

RFNoC protocol version.

Offset 0x0020: RADIO_TIME_LOW Register (R) 🔗

(showhide extended info)

0x000020

RADIO_TIME_LOW

offset=0x0020

Total Offset =

0x000040

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the lower 32 bits of the current radio time. Read the LOW register followed by the HIGH register to get a coherent 64-bit value.

Offset 0x0024: RADIO_TIME_HIGH Register (R) 🔗

(showhide extended info)

0x000020

RADIO_TIME_HIGH

offset=0x0024

Total Offset =

0x000044

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the upper 32 bits of the radio time from when the LOW register was read. Read the LOW register followed by the HIGH register to get a coherent 64-bit value.

Offset 0x0028: INT_PPS_DIVIDER Register (R|W) 🔗

(showhide extended info)

0x000020

INT_PPS_DIVIDER

offset=0x0028

Total Offset =

0x000048

Initial Value = 0x07530000

This register is defined in HDL source file core_regs.sv.

Controls the divider for the internal PPS generator.

31..0

INT_PPS_DIV (initialvalue=122880000)

Divider value for internal PPS generator.

Offset 0x002C: CORE_NUM_TIMEKEEPERS Register (R) 🔗

(showhide extended info)

0x000020

CORE_NUM_TIMEKEEPERS

offset=0x002C

Total Offset =

0x00004C

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Reports the number of timekeepers in the system.

31..0

CORE_NUM_TIMEKEEPERS_VAL

Number of timekeepers in the system.

Offset 0x0030: CORE_BUILD_SEED Register (R) 🔗

(showhide extended info)

0x000020

CORE_BUILD_SEED

offset=0x0030

Total Offset =

0x000050

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Holds the build seed for the current FPGA build.

31..0

CORE_BUILD_SEED_VAL

Build seed value.

Offset 0x0034: FP_GPIO_SRC Register (R|W) 🔗

(showhide extended info)

0x000020

FP_GPIO_SRC

offset=0x0034

Total Offset =

0x000054

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Controls the source of the front panel GPIOs.

Bits	Name
31..24	Reserved
23..20	Reserved
19..18	FP_GPIO9_SRC Source for front panel GPIO9. 0 = CH0_ATR, 1 = CH1_ATR.
17..16	FP_GPIO8_SRC Source for front panel GPIO8. 0 = CH0_ATR, 1 = CH1_ATR.
15..14	FP_GPIO7_SRC Source for front panel GPIO7. 0 = CH0_ATR, 1 = CH1_ATR.
13..12	FP_GPIO6_SRC Source for front panel GPIO6. 0 = CH0_ATR, 1 = CH1_ATR.
11..10	FP_GPIO5_SRC Source for front panel GPIO5. 0 = CH0_ATR, 1 = CH1_ATR.
9..8	FP_GPIO4_SRC Source for front panel GPIO4. 0 = CH0_ATR, 1 = CH1_ATR.
7..6	FP_GPIO3_SRC Source for front panel GPIO3. 0 = CH0_ATR, 1 = CH1_ATR.
5..4	FP_GPIO2_SRC Source for front panel GPIO2. 0 = CH0_ATR, 1 = CH1_ATR.
3..2	FP_GPIO1_SRC Source for front panel GPIO1. 0 = CH0_ATR, 1 = CH1_ATR.
1..0	FP_GPIO0_SRC Source for front panel GPIO0. 0 = CH0_ATR, 1 = CH1_ATR.

Offset 0x0038: GPS_CTRL Register (R|W) 🔗

(showhide extended info)

0x000020

GPS_CTRL

offset=0x0038

Total Offset =

0x000058

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Controls GPIO lines to the GPS circuits.

Bits	Name
31..24	Reserved
23..21	Reserved
20	GPS_BYPASS_LMK Allows using the PPS signal directly from the GPS chip instead of the LMK05318 when using the GPSDO. 0 = LMK05318 is used to generate the GPS PPS signal. 1 = Use PPS signal from an GPS chip.
19..17	Reserved
16	GPS_LMK_GPIO Controls output to the LMK05318's GPIO0/SYNCN line.
15..14	Reserved
13..12r	GPS_LMK_STATUS Reports the state of the status indicators from the LMK05318.
11..9	Reserved
8r	GPS_LMK_PPS_MONITOR This bit toggles on the rising edge of the GPS LMK PPS signal. Can be used to monitor the GPS LMK PPS signal in software.
7..5	Reserved
4r	GPS_PW_FAULT Read-only bit that indicates an overcurrent fault on the GPS power for active antennas.
3..2	Reserved
1	REG_GPS_ANT_PWR_EN 0 = GPS antenna power disabled. 1 = GPS antenna power enabled.
0	REG_GPS_RESET_N 0 = GPS in reset. 1 = GPS out of reset.

Offset 0x003C: TEMP_MON Register (R) 🔗

(showhide extended info)

0x000020

TEMP_MON

offset=0x003C

Total Offset =

0x00005C

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Reports values from the FPGA temperature monitor.

Bits	Name
31..24	Reserved
23..16	Reserved
15..12	Reserved
11..0	DEVICE_TEMP Current FPGA temperature. To convert to degrees Celsius, use the formula: Temp (C) = [(DEVICE_TEMP x 503.975) / 4096 - 273.15]

Offset 0x0040: LMK_SYNC_CTRL Register (R|W) 🔗

(showhide extended info)

0x000020

LMK_SYNC_CTRL

offset=0x0040

Total Offset =

0x000060

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Bits	Name
31	LMK_CLKIN0_SYNC_SEL REVA sets this to 0 to select SYNC pin as syc pin with not as good setup/hold time. REVB sets this to 1 to select ClkIN0 pin as sync pin with better setup/hold time. When setting this pin to 1, then 1 needs subtracted from the @PPS_IN_TO_RCLK_DELAY field as the LMK has one register delay on ClkIN0 vs Sync.
30	LMK_SYNC_CLK_SEL Set to 0 to make lmk sync output synchronous to radio_clk (for clock distribution mode) Set to 1 to make lmk sync output synchronous to ref_clk (for ext 10MHz ref in) - "0" needed for clock distribution mode to meet setup/hold of flip flop inside the LMK04832 synchronous to ref_clk. Not intuitive this is needed, but reason why timing is better is radio_clk is from a pll where ref_clk is from an IO buffer with large delay. - "1" needed for external 10MHz mode because during synchronization the radio_clk looses lock due to clk0 being reset. Thus sync needs driven from active ref_clk. It is easy to meet timing to LMK with 10MHz clock due to it having a 100ns period.
29r	LMK_SYNC_DONE Indicates the success of the PLL reset started by @.PLL_SYNC_TRIGGER. Reset on deassertion of @.PLL_SYNC_TRIGGER.
28	LMK_SYNC_TRIGGER Assertion triggers the SYNC signal generation for LMK04832 after the next appearance of the PPS rising edge. There is no self reset on this trigger. Keep this trigger asserted until @.PLL_SYNC_DONE is asserted.
27	Reserved
26..0	LMK_SYNC_DELAY Controls the delay from PPS_IN to LMK_SYNC being sent to the LMK chip in in ext_ref_clk cycles.

Offset 0x0044: PPS_IN_CTRL Register (R|W) 🔗

(showhide extended info)

0x000020

PPS_IN_CTRL

offset=0x0044

Total Offset =

0x000064

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..10	Reserved
9..0	PPS_IN_TO_RCLK_DELAY

Offset 0x0048: TBOLT_CTRL Register (R|W) 🔗

(showhide extended info)

0x000020

TBOLT_CTRL

offset=0x0048

Total Offset =

0x000068

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Control register for Thunderbolt controller resets.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..1	Reserved
0w	TBOLT_PD_CTRL_PULSE_RST (Strobe) Writing a 1 to this bit will pulse the reset line to the Thunderbolt PD controller, forcing the FPGA to reconfigure. There's is a 500ms delay before the pulse is generated to allow software to service the write transaction and return an ACK before the FPGA resets.

Offset 0x004C: POWER_CONTROL_STS Register (R|W) 🔗

(showhide extended info)

B310_RADIO_REGMAP|RADIO_SPI_WINDOW

0x000020

POWER_CONTROL_STS

offset=0x004C

Total Offset =

0x00006C

Initial Value not specified

This register is defined in HDL source file core_regs.sv.

Control/status register for power signals

Bits	Name
31..24	Reserved
23..16	Reserved
15..9	Reserved
8	POWER_LED_OVERRIDE Control for power status LED. 0 = Blue if powered up, 1 = force orange.
7..6	Reserved
5r	TYPEC_POWER_NEGOTIATED Indicates if the USB Type-C power negotiation has completed successfully.
4r	POWER_25W_SRC Indicates if an external source is providing 25W of power to the device. 0: Power is provided by PCIe slot, 1: Power is provided by external source.
3..2	Reserved
1r	POWER_MONITOR_ALERT Indicates if the INA219 power monitor has asserted an alert.
0r	POWER_GOOD_1V2 Status of 1.2V power supply.

CTRLPORT_SPI_ADRV_REGMAP 🔗

Settings registers for the ADRV SPI engine. The SCLK rate is fixed by the HALF_PER parameter; no software-programmable clock divider register is present in this configuration.

Offset 0x0004: REG_SI Register (W) 🔗

(showhide extended info)

0x000100

REG_SI

offset=0x0004

Total Offset =

0x000104

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Single-instruction register. Writing this register immediately triggers a 3-byte SPI transaction ([addr_hi, addr_lo, data_byte]) without needing to write REG_CONTROL or REG_DATA. Direction is set by bit 7 of SI_ADDR_HI (ADI ADRV R/W# bit): 0 = write, 1 = read. For reads, the 3 received bytes are placed in the RX FIFO and can be read back via REG_DATA.

Bits	Name
31..24	Reserved
23..16w	SI_DATA_BYTE Third byte on the wire (data byte).
15..8w	SI_ADDR_LO Second byte on the wire (low byte of the SPI address).
7..0w	SI_ADDR_HI First byte on the wire (high byte of SPI address). Bit 7 is the R/W# direction bit.

Offset 0x003C: REG_CONTROL Register (W) 🔗

(showhide extended info)

B310_RADIO_REGMAP|RADIO_SPI_WINDOW

0x000100

REG_CONTROL

offset=0x003C

Total Offset =

0x00013C

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Transaction control register. Writing this register starts a new SPI transaction.

Bits	Name
31w	SPI_DIR Transfer direction: 0 = write, 1 = read.
30	Reserved
29..28w	SPI_MODE Transaction mode: 0 = RAW, 1 = SI_SEQ, 2 = SI_REP, 3 = STREAMING.
27..16w	SPI_NUM_BYTES Number of data bytes to transfer.
15..0w	SPI_ADDR 16-bit SPI register address. Used in SI_SEQ, SI_REP, and STREAMING modes.

Offset 0x0040: REG_DATA Register (R|W) 🔗

(showhide extended info)

B310_RADIO_REGMAP|RADIO_SPI_WINDOW

0x000100

REG_DATA

offset=0x0040

Total Offset =

0x000140

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Data window (16 words, 64 bytes). Any address in 0x40..0x7F maps to this virtual register. When transmitted over SPI, the first byte on the wire is taken from [7:0], the second byte from [15:8], and so on. Write: Load the next 32-bit word into the TX FIFO. The CtrlPort ACK is not asserted until the word is accepted. Read: Return the next 32-bit word from the RX FIFO. The CtrlPort does not respond to the read until the data is available.

31..0

SPI_DATA

32-bit data word (first byte in least-significant position).

CTRLPORT_TO_SIMPLE_SPI_REGMAP 🔗

This regmap contains the settings registers for the SPI engine.

Offset 0x0000: SCLK_DIVIDER Register (R|W) 🔗

(showhide extended info)

0x0000A0

SCLK_DIVIDER

offset=0x0000

Total Offset =

0x0000A0

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Controls clock rate for subsequent SPI transactions.

Bits	Name
31..24	Reserved
23..17	Reserved
16	FORCE_SS Force the slave select line to be active regardless of the state of the SPI transaction. This allows for sending longer transactions without having to wait for the slave select line to be deasserted.
15..0	SPI_CLK_DIV Clock Divider. f_sclk = f_radio_clk / (2 * (SPI_CLK_DIV + 1))

Offset 0x0004: SPI_PERSONALITY Register (R|W) 🔗

(showhide extended info)

0x0000A0

SPI_PERSONALITY

offset=0x0004

Total Offset =

0x0000A4

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Controls the personality of the SPI transaction.

Bits	Name
31	SPI_MOSI_EDGE Controls the edge in which the MOSI line is updated. 0 = falling edge of SCLK. 1 = rising edge of SCLK.
30	SPI_MISO_EDGE Controls the edge in which the MISO line is sampled. 0 = falling edge of SCLK. 1 = rising edge of SCLK.
29..24	SPI_NUM_BITS Number of bits to transfer in the SPI transaction. The actual length is SPI_NUM_BITS+1.
23..0	SPI_SLAVE_SELECT Controls which slaves are selected for the SPI transaction. Each bit corresponds to a slave, starting with slave 0.

Offset 0x0008: SPI_MOSI_DATA Register (W) 🔗

(showhide extended info)

0x0000A0

SPI_MOSI_DATA

offset=0x0008

Total Offset =

0x0000A8

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Controls the data to be sent on the MOSI line.

31..0w

SPI_DATA_OUT

The data to be sent on the MOSI line. This data is shifted out starting from bit 31, so it is MSB aligned. Writing this register will trigger a SPI transaction.

Offset 0x000C: SPI_STATUS Register (R) 🔗

(showhide extended info)

0x0000A0

SPI_STATUS

offset=0x000C

Total Offset =

0x0000AC

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Contains the status for the SPI ENGINE.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..1	Reserved
0	SPI_READY Indicates if the SPI engine is ready for a new transaction.

Offset 0x0010: SPI_READBACK Register (R) 🔗

(showhide extended info)

0x0000A0

SPI_READBACK

offset=0x0010

Total Offset =

0x0000B0

Initial Value not specified

This register is defined in HDL source file b310_core.sv.

Contains the readback data from the last SPI transaction.

31..0

SPI_READBACK_DATA

Contains the readback data from the last SPI transaction. The data is shifted in starting from bit 0, so it is in-order. This register is updated when the SPI transaction is done.

RADIO_CONTROL_REGMAP 🔗

RADIO_CONTROL_REGS 🔗

Offset 0x0000: MISC_OUTPUTS Register (R|W) 🔗

(showhide extended info)

0x000000

MISC_OUTPUTS

offset=0x0000

Total Offset =

0x000000

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.

This register contains the miscellaneous control for the analog path.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..2	Reserved
1	ADRV9032_TEST_EN Controls test mode for ADRV9032 chip. 0 = normal operation, 1 = test mode
0	ADRV9032_RESET Controls reset line to ADRV9032 chip. 0 = reset, 1 = normal operation

Offset 0x0004: MISC_INPUTS Register (R) 🔗

(showhide extended info)

0x000000

MISC_INPUTS

offset=0x0004

Total Offset =

0x000004

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.

Status register for miscellaneous inputs.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..2	Reserved
1	ADRV_INTERRUPT_1 Status of ADRV9032 interrupt line 1.
0	ADRV_INTERRUPT_0 Status of ADRV9032 interrupt line 0.

Offset 0x0010: CH0_LED_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH0_LED_ATR

offset=0x0010

Total Offset =

0x000010

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_LED_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channels LED values given the channel's ATR state. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Controls the LEDs state for channel 0 given the channel's ATR state.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..5	Reserved
4w	LED_RX_GREEN Controls the RX green LED state. 0 = off, 1 = on
3..2	Reserved
1w	LED_TX_RED Controls the TX red LED state. 0 = off, 1 = on
0w	LED_TX_GREEN Controls the TX green LED state. 0 = off, 1 = on

Offset 0x0018: CH0_LED_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH0_LED_STATUS

offset=0x0018

Total Offset =

0x000018

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_LED_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..5	Reserved
4	LED_RX_GREEN Controls the RX green LED state. 0 = off, 1 = on
3..2	Reserved
1	LED_TX_RED Controls the TX red LED state. 0 = off, 1 = on
0	LED_TX_GREEN Controls the TX green LED state. 0 = off, 1 = on

Offset 0x0020: CH1_LED_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH1_LED_ATR

offset=0x0020

Total Offset =

0x000020

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_LED_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..5	Reserved
4w	LED_RX_GREEN Controls the RX green LED state. 0 = off, 1 = on
3..2	Reserved
1w	LED_TX_RED Controls the TX red LED state. 0 = off, 1 = on
0w	LED_TX_GREEN Controls the TX green LED state. 0 = off, 1 = on

Offset 0x0028: CH1_LED_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH1_LED_STATUS

offset=0x0028

Total Offset =

0x000028

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_LED_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..5	Reserved
4	LED_RX_GREEN Controls the RX green LED state. 0 = off, 1 = on
3..2	Reserved
1	LED_TX_RED Controls the TX red LED state. 0 = off, 1 = on
0	LED_TX_GREEN Controls the TX green LED state. 0 = off, 1 = on

Offset 0x0030: CH0_FP_GPIO_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH0_FP_GPIO_ATR

offset=0x0030

Total Offset =

0x000030

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_FP_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channel's HDMI GPIO drive values based on the channel's ATR state. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Controls the HDMI GPIO drive values for channel 0 based on the channel's ATR state

Bits	Name
31..24	Reserved
23..16	Reserved
15..10	Reserved
9..0w	FP_DRIVE_VALUES Controls the HDMI GPIO drive values for the channel.

Offset 0x0038: CH0_FP_GPIO_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH0_FP_GPIO_STATUS

offset=0x0038

Total Offset =

0x000038

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_FP_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..10	Reserved
9..0	FP_DRIVE_VALUES Controls the HDMI GPIO drive values for the channel.

Offset 0x0040: CH1_FP_GPIO_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH1_FP_GPIO_ATR

offset=0x0040

Total Offset =

0x000040

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_FP_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..10	Reserved
9..0w	FP_DRIVE_VALUES Controls the HDMI GPIO drive values for the channel.

Offset 0x0048: CH1_FP_GPIO_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH1_FP_GPIO_STATUS

offset=0x0048

Total Offset =

0x000048

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_FP_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..10	Reserved
9..0	FP_DRIVE_VALUES Controls the HDMI GPIO drive values for the channel.

Offset 0x0050: CH0_ADRV_GPIO_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH0_ADRV_GPIO_ATR

offset=0x0050

Total Offset =

0x000050

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_ADRV_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channel's ADRV TRX drive values based on the channel's ATR state. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Controls the ADRV TRX GPIO drive values for channel 0 based on the channel ATR state.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7w	ADRV_GPIO_3 Controls fourth ADRV GPIO line for the channel.
6w	ADRV_GPIO_2 Controls third ADRV GPIO line for the channel.
5w	ADRV_GPIO_1 Controls second ADRV GPIO line for the channel.
4w	ADRV_GPIO_0 Controls first ADRV GPIO line for the channel.
3w	TRX_CTRL_3 Controls fourth ADRV TRX line for the channel.
2w	TRX_CTRL_2 Controls third ADRV TRX line for the channel.
1w	TRX_CTRL_1 Controls second ADRV TRX line for the channel.
0w	TRX_CTRL_0 Controls first ADRV TRX line for the channel.

Offset 0x0058: CH0_ADRV_GPIO_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH0_ADRV_GPIO_STATUS

offset=0x0058

Total Offset =

0x000058

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_ADRV_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channel's ADRV TRX drive values based on the channel's ATR state. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Reads the ADRV TRX GPIO drive values for channel 0.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7	ADRV_GPIO_3 Controls fourth ADRV GPIO line for the channel.
6	ADRV_GPIO_2 Controls third ADRV GPIO line for the channel.
5	ADRV_GPIO_1 Controls second ADRV GPIO line for the channel.
4	ADRV_GPIO_0 Controls first ADRV GPIO line for the channel.
3	TRX_CTRL_3 Controls fourth ADRV TRX line for the channel.
2	TRX_CTRL_2 Controls third ADRV TRX line for the channel.
1	TRX_CTRL_1 Controls second ADRV TRX line for the channel.
0	TRX_CTRL_0 Controls first ADRV TRX line for the channel.

Offset 0x0060: CH1_ADRV_GPIO_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH1_ADRV_GPIO_ATR

offset=0x0060

Total Offset =

0x000060

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_ADRV_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7w	ADRV_GPIO_3 Controls fourth ADRV GPIO line for the channel.
6w	ADRV_GPIO_2 Controls third ADRV GPIO line for the channel.
5w	ADRV_GPIO_1 Controls second ADRV GPIO line for the channel.
4w	ADRV_GPIO_0 Controls first ADRV GPIO line for the channel.
3w	TRX_CTRL_3 Controls fourth ADRV TRX line for the channel.
2w	TRX_CTRL_2 Controls third ADRV TRX line for the channel.
1w	TRX_CTRL_1 Controls second ADRV TRX line for the channel.
0w	TRX_CTRL_0 Controls first ADRV TRX line for the channel.

Offset 0x0068: CH1_ADRV_GPIO_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH1_ADRV_GPIO_STATUS

offset=0x0068

Total Offset =

0x000068

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_ADRV_GPIO_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channel's ADRV TRX drive values based on the channel's ATR state. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Reads the ADRV TRX GPIO drive values for channel 1.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7	ADRV_GPIO_3 Controls fourth ADRV GPIO line for the channel.
6	ADRV_GPIO_2 Controls third ADRV GPIO line for the channel.
5	ADRV_GPIO_1 Controls second ADRV GPIO line for the channel.
4	ADRV_GPIO_0 Controls first ADRV GPIO line for the channel.
3	TRX_CTRL_3 Controls fourth ADRV TRX line for the channel.
2	TRX_CTRL_2 Controls third ADRV TRX line for the channel.
1	TRX_CTRL_1 Controls second ADRV TRX line for the channel.
0	TRX_CTRL_0 Controls first ADRV TRX line for the channel.

Offset 0x0070: CH0_PATH_CTRL_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH0_PATH_CTRL_ATR

offset=0x0070

Total Offset =

0x000070

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_PATH_CTRL_ATR which is defined in HDL source file radio_control_regs.sv.

Controls one channel's path control signals. This is the base offset of 6 different registers: BASE+0 DEFAULT_IDLE BASE+1 RX_ACTIVE BASE+2 TX_ACTIVE BASE+3 FDX BASE+4 DDR BASE+5 ATR_DISABLED
Controls the path control signals for channel 0 based on the channel's ATR state.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..2	Reserved
1w	CH_BYPASS_RX Controls RX bypass switch. 1 = bypass, 0 = RX enabled
0w	CH_ENABLE_TXRX_TDR Controls FE TDR switch.

Offset 0x0078: CH0_PATH_CTRL_STATUS Register (R) 🔗

(showhide extended info)

0x000000

CH0_PATH_CTRL_STATUS

offset=0x0078

Total Offset =

0x000078

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_PATH_CTRL_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..2	Reserved
1	CH_BYPASS_RX Controls RX bypass switch. 1 = bypass, 0 = RX enabled
0	CH_ENABLE_TXRX_TDR Controls FE TDR switch.

Offset 0x0080: CH1_PATH_CTRL_ATR Register (W) 🔗

(showhide extended info)

0x000000

CH1_PATH_CTRL_ATR

offset=0x0080

Total Offset =

0x000080

Initial Value not specified

This register is defined in HDL source file radio_control_regs.sv.
It uses RegType CH_PATH_CTRL_ATR which is defined in HDL source file radio_control_regs.sv.

Bits	Name
31..24	Reserved
23..16	Reserved
15..8	Reserved
7..2	Reserved
1w	CH_BYPASS_RX Controls RX bypass switch. 1 = bypass, 0 = RX enabled
0w	CH_ENABLE_TXRX_TDR Controls FE TDR switch.

Offset 0x0088: CH1_PATH_CTRL_STATUS Register (R) 🔗

(showhide extended info)